The evidence behind each calculator's numbers, with the working shown.
The checks behind each calculator, in two kinds.
Independent evidence
The answer matches a figure worked out independently: a hand calculation, a published example, a field solver, SPICE, or an engineering expectation. Each case names its source.
Self-consistency
The answer matches a stored snapshot, so any unintended change is caught. This shows the answer is stable, so it is counted separately from independent evidence.
Published so you can check it yourself. A design aid, not a certification.
Evidence summary
Calculators
36
With independent evidence
25of 36
Independent cases agreeing
65 / 65
Checked against a stored result
11
Sources listed in full
11
Accuracy stated
13
Engine version
v1.18.3
Every case runs with each release, so the Computed column is what this version produces.
Smallest allowed pull-up for a 3 mA sink at 0.4 V on 3.3 VR = (V_DD - V_OL)/I_OL: (3.3 - 0.4)/0.003 = 966.6666667 Ω.
Hand computation
966.667
966.667
< 0.001 %to the last figure
Largest allowed pull-up for 100 pF in fast modeNXP UM10204: R = t_r/(0.8473 C_b), where 0.8473 = ln(7/3), the 30 % to 70 % rise of an RC. With t_r = 300 ns: 300e-9/(0.8473 x 100e-12) = 3540.6585 Ω.
Hand computation
3540.66
3540.66
< 0.001 %to the last figure
The E24 value at the centre of that windowGeometric centre sqrt(966.667 x 3540.659) = 1850.0 Ω. Of its E24 neighbours, 1.8 k and 2 k, it is nearer 1.8 k on a linear or a log scale.
Non-inverting gain with 10 k over 1 kG = 1 + R_f/R_1: 1 + 10000/1000 = 11 exactly.
Hand computation
11
11
0 %to the last figure
Closed-loop bandwidth of that stage on a 10 MHz partGain-bandwidth product divided by the noise gain, which here equals the signal gain: 10e6/11 = 909090.909 Hz.
Hand computation
909091
909091
< 0.001 %to the last figure
An inverting stage of gain 10 still has a noise gain of 11An inverting stage divides the gain-bandwidth product by 1 + R_f/R_1, not by its own gain. Same resistors, so the bandwidth is still 10e6/11.
Method fromJEDEC JESD51-2, Integrated Circuits Thermal Test Method, still air
AccuracyThe dissipation is exact arithmetic. Junction temperature and the current limit are only as good as R_thetaJA, which depends on the board as much as the package.
Case
Kind of evidence
Expected
Computed
Difference
5 V to 3.3 V at 250 mA with 50 µA quiescentP = (V_in - V_out) I_out + V_in I_q: (5 - 3.3) x 0.25 + 5 x 50e-6 = 0.42525 W exactly.
Method fromSmith, Anderson, Forehand, Pelc and Roy, Power distribution system design methodology and capacitor selection for modern CMOS technology, IEEE Transactions on Advanced Packaging (1999); Smith and Bogatin, Principles of Power Integrity for PDN Design Simplified
AccuracyA lumped network with exact arithmetic, so the error lies in the inductances you enter. Mounting inductance spans roughly 0.3 to 2 nH for ordinary pads and vias and sets the answer above about 30 MHz, so the verdict uses the worst-case value.
Case
Kind of evidence
Expected
Computed
Difference
3 % of 0.9 V under a 10 A stepZ = V r / dI: 0.9 x 0.03 / 10 = 0.0027 Ω exactly.
Hand computation
0.0027
0.0027
0 %to the last figure
50 cm² of plane pair on 0.1 mm of Er 4.3C = e0 Er A / h: 8.8541878128e-12 x 4.3 x 50e-4 / 1e-4 = 1.90365038e-9 F.
Hand computation
1.90365e-9
1.90365e-9
< 0.001 %to the last figure
Spreading inductance to a group 3 mm from the loadL = (mu0 h / 2 pi) ln(d / r_v): the prefactor is 2e-7 x 1e-4 = 2e-11 H and ln(3 mm / 0.15 mm) = ln(20) = 2.995732274, so L = 5.99146455e-11 H.
Hand computation
5.99146e-11
5.99146e-11
< 0.001 %to the last figure
First cavity mode of a 100 mm plane on Er 4.3f = c0 / (2 a sqrt(Er)): 299792458 / (2 x 0.1 x 2.073644135) = 7.22863805e8 Hz.
Hand computation
722864000
722864000
< 0.001 %to the last figure
The inductance floor of all three groups togetherEach branch is (ESL + L_mount)/N plus its spreading term, at the worst-case 2 nH mount: 1.89914645e-10, 4.62640533e-10 and 2.35596635e-9 H. In parallel, 1.27364474e-10 H. The capacitance derating does not enter: the floor is set by inductance alone.
Hand computation
1.27364e-10
1.27364e-10
< 0.001 %to the last figure
The in-band peak used for the verdict, without the lumped-plane artefactAnti-resonance of the 2 µH regulator branch with the derated bulk capacitance: 2.442 Ω near 9.4 kHz, computed separately from the same network. The full sweep also peaks at 11.95 Ω near 320 MHz. That peak is the ideal lossless plane capacitor ringing against the bank inductance, an artefact of lumping a distributed plane into two elements. Remove the plane branch and the peak is still 2.442 Ω.The peak is taken on a discrete log grid, so it is quoted to four figures and checked to 0.1 %.
Hand computation
2.442
2.4422
0.00832 %±0.1 %
The frequency above which no capacitor on this board helpsf = Z_target / (2 pi L_node): 0.0027 / (2 pi x 1.27364474e-10) = 3.37392629e6 Hz. Both inputs are checked in the cases above.
Method fromAllegro MicroSystems AN295014 Rev. 1, Computing IC Temperature Rise, Eq. 1 (2022); JEDEC JESD51-2, Integrated Circuits Thermal Test Method, still air
AccuracyThe equation is exact arithmetic. The uncertainty is all in R_θ, which depends on the board as much as the package: a datasheet figure from a JEDEC test board can be a factor of two off on yours.
Case
Kind of evidence
Expected
Computed
Difference
0.5 W in a 125 °C/W package at 70 °C ambientT_J = T_A + P R: 70 + 0.5 x 125 = 132.5 °C exactly.
Hand computation
132.5
132.5
0 %to the last figure
Allowable dissipation for the same packageP = (T_Jmax - T_A)/R: (150 - 70)/125 = 0.64 W exactly.
Method fromAllegro MicroSystems AN295014 Rev. 1, Computing IC Temperature Rise, Eq. 2–4 (2022)
Case
Kind of evidence
Expected
Computed
Difference
Logic power of four channels at 5.25 V and 25 mAP = n V_CC I_CC: 4 x 5.25 x 0.025 = 0.525 W exactly.
Hand computation
0.525
0.525
0 %to the last figure
Both stages together, driving 250 mA at 0.7 V saturationThe output stage adds n V_CE(sat) I_C = 4 x 0.7 x 0.25 = 0.7 W, so the instantaneous ON power is 0.525 + 0.7 = 1.225 W exactly.
Hand computation
1.225
1.225
0 %to the last figure
OFF power: 7.5 mA of logic and 0.1 mA of leakage at 100 VP = n V_CC I_CC(off) + n V_off I_leak: 4 x 5.5 x 0.0075 + 4 x 100 x 0.0001 = 0.165 + 0.04 = 0.205 W exactly.
Hand computation
0.205
0.205
0 %to the last figure
Allowable average power for the package at 85 °CP = (T_Jmax - T_A)/R: (150 - 85)/100 = 0.65 W exactly.
Method fromJEDEC JESD51-2, Integrated Circuits Thermal Test Method, still air
AccuracyResistances in series, exact in steady state only. Each term is as good as its source: junction to case is the tightest, the interface the loosest, and sink to air depends on the real airflow.
Case
Kind of evidence
Expected
Computed
Difference
5 W through 1.5 + 0.5 + 4 °C/W from 50 °C ambientSeries thermal resistances add: T_J = T_A + P(R_JC + R_CS + R_SA) = 50 + 5 x 6 = 80 °C exactly.The panel shows node temperatures to one decimal, so the check cannot be tighter.
Hand computation
80
80
0 %±0.1 %
The heat sink that holds a 25 W part 25 °C below its 150 °C limitR_SA = (T_des - T_A)/P - R_JC - R_CS, with T_des = 150 - 25 = 125 °C: (125 - 45)/25 - 1.0 = 3.2 - 1.0 = 2.2 °C/W exactly.
Method fromJESD51-14, Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction to Case of Semiconductor Devices with a Single Heat Flow Path; JESD51-1, Integrated Circuit Thermal Measurement Method, Electrical Test Method
AccuracyExact closed-form arithmetic, with nothing fitted. The error is in the R and tau set and how it was measured: a junction-to-case set assumes an isothermal case, a junction-to-ambient set the JEDEC test board in still air.
Case
Kind of evidence
Expected
Computed
Difference
One Foster stage of 1 °C/W and 1 s, after one time constantZ = R(1 - e^(-t/tau)): 1 - e^-1 = 0.6321205588 °C/W. A wrong sign or an inverted tau breaks this first.
Hand computation
0.632121
0.632121
< 0.001 %to the last figure
20 W into that stage for 1 s, from 25 °CT = T_ref + P Z: 25 + 20 x 0.6321205588 = 37.64241118 °C.
Hand computation
37.6424
37.6424
< 0.001 %to the last figure
The same stage at 50 per cent duty, in steady stateThe periodic form gives (1 - e^-1)/(1 - e^-2). The denominator factorises as (1 - e^-1)(1 + e^-1), which leaves 1/(1 + e^-1) = 0.7310585786 °C/W.
Hand computation
0.731059
0.731059
< 0.001 %to the last figure
The application-note approximation for the same caseD R + (1 - D) Z(t_p): 0.5 x 1 + 0.5 x 0.6321205588 = 0.8160602794 °C/W, against the exact 0.7310585786. The page shows both.
Method fromIPC-2221B, Generic Standard on Printed Board Design, §6.2 (2012)
AccuracyA curve fit to measurements on bare boards in still air. A plane underneath runs cooler; a sealed enclosure runs hotter. Use it as a starting width.
Case
Kind of evidence
Expected
Computed
Difference
3 A at a 20 °C rise on an external 1 oz layerIPC-2221 solved for area: A = (3/(0.048 x 20^0.44))^(1/0.725) = 48.70 mil²; at 1.37 mil thick that is 35.55 mil, or 0.9029 mm wide.The hand figure is rounded to four places.
Hand computation
0.9029
0.9028
-0.0111 %±0.2 %
Doubling the current widens the trace about 2.6 timesThe IPC exponent is 1/0.725, so width scales as I^1.379: 2^1.379 = 2.60. A result near 2 or near 4 would be wrong.0.9029 mm x 2.60. A loose band: it checks the shape of the law, not the digits.
Resistance of 50 mm of 1 mm wide 1 oz copper at 25 °CR = rho l/(w t), with rho = 1.724e-8 Ω m at 20 °C and alpha = 0.00393: 50 squares of 34.8 µm copper give about 24.8 mΩ at 25 °C.The hand figure rounds the copper thickness. Two per cent covers it.
Method fromIPC-2221B, Generic Standard on Printed Board Design, §6.2 (2012)
AccuracyThe IPC-2221 trace curve applied to the barrel cross-section. It ignores the heat the barrel sheds into the planes it crosses, so the current it reports is conservative.
Case
Kind of evidence
Expected
Computed
Difference
Copper in the barrel of a 0.3 mm hole plated 25 µmThe barrel is an annulus, taken at its mean diameter: A = pi (d + t_p) t_p = pi x 0.325 mm x 0.025 mm = 0.02552544 mm².
Hand computation
0.0255254
0.0255254
< 0.001 %to the last figure
Resistance of that barrel through a 1.6 mm board at 25 °CR = rho l/A, with rho = 1.724e-8 Ω m at 20 °C and alpha = 0.00393: 1.75788e-8 x 1.6e-3 / 2.552544e-8 = 1.10188e-3 Ω.The hand figure is rounded to six places.
Method fromHammerstad and Jensen, Accurate Models for Microstrip Computer-Aided Design (1980); Cohn, Characteristic Impedance of the Shielded-Strip Transmission Line (1954)
AccuracyClosed-form fits to the exact static solution. Within their range, ε_r (quoted at one frequency, not yours) and etch tolerance move the answer more than model error does. Use the tolerance analysis to see the band.
Case
Kind of evidence
Expected
Computed
Difference
50 Ω microstrip on 0.11 mm prepreg over a planeRule of thumb: a 50 Ω microstrip on FR-4 is about twice as wide as its dielectric is thick. This checks the band, not the digits.The rule of thumb is good to about twelve per cent, no better.
Engineering expectation
50
48.4
-3.2 %±12 %
A wider trace has a lower impedanceImpedance falls as the trace widens, in every transmission-line model. This catches a sign error.A wide band: it checks the direction and the order of magnitude.
Engineering expectation
32
31.6
-1.25 %±25 %
Alumina, w/h = 1, zero copper thicknessHammerstad and Jensen’s equations, worked in a separate script without the engine. This checks the code against the method, not the method itself.One per cent: the tightest check on this calculator.
The cross-section of 18 AWGAWG is a geometric series, d = 0.127 mm x 92^((36-n)/39): 18 AWG is 1.0238 mm across, so pi d^2/4 = 0.8232 mm². Wire tables give 0.823 mm², and a gauge off by one would show at once.The panel and the wire tables both give three figures.
Engineering expectation
0.823
0.823
0 %±0.3 %
Resistance of 2 m of 18 AWG, there and back, at 20 °CR = rho l/A over 4 m of conductor: 1.724e-8 x 4 / 8.2316e-7 = 0.083775 Ω. Handbooks give about 20.95 Ω/km for 18 AWG, which is 0.0838 Ω for 4 m.
Ring left by a 0.6 mm pad on a 0.3 mm holeHalf the difference of the diameters: (0.6 - 0.3)/2 = 0.15 mm exactly.
Hand computation
0.00015
0.00015
0 %to the last figure
The ring left when the drill lands 50 µm off centreThe whole hole shifts, so the ring loses the full registration on one side: 0.15 - 0.05 = 0.10 mm exactly. Halving the shift is the optimistic mistake.
Hand computation
0.0001
0.0001
< 0.001 %to the last figure
The smallest pad this hole can have and still pass the fabD + 2(ring_min + t_reg): 0.3 + 2 x (0.125 + 0.05) = 0.3 + 0.35 = 0.65 mm exactly. That is larger than the 0.6 mm pad drawn, so the drawn pad is too small.
Method fromWheeler, Formulas for the Skin Effect, Proceedings of the IRE (1942); Hammerstad and Jensen, Accurate Models for Microstrip Computer-Aided Design (1980); Hammerstad and Bekkadal, A Microstrip Handbook, University of Trondheim
AccuracyDielectric loss is exact for stripline. For microstrip the √ε_eff form leaves out the filling factor, so it overstates dielectric loss somewhat, on the safe side. Conductor loss uses Wheeler’s rule, which reproduces the exact coaxial result. Foil roughness and the loss tangent at your frequency move the answer most, so roughness is shown as a band and the verdict uses its rough end.
Case
Kind of evidence
Expected
Computed
Difference
Skin depth in copper at 5 GHzd = sqrt(rho / (pi f mu0)), with rho = 1.724e-8 Ω m: sqrt(1.724e-8 / (pi x 5e9 x 4pi e-7)) = 9.34552622e-7 m. At 1 GHz the same formula gives 2.09 µm, the textbook figure.
Hand computation
9.34553e-7
9.34553e-7
< 0.001 %to the last figure
DC resistance of a 0.2 mm wide, 1 oz trace at 20 °CR = rho / (w t), with 1 oz of finished copper taken as 34.8 µm: 1.724e-8 / (2e-4 x 3.48e-5) = 2.47701149 Ω/m.
Hand computation
2.47701
2.47701
< 0.001 %to the last figure
Hammerstad roughness factor for 0.4 µm foil at 5 GHzK = 1 + (2/pi) arctan(1.4 (D/d)^2): D/d = 0.4/0.934552622 = 0.42801, squared is 0.183193, times 1.4 is 0.256470, arctan is 0.250996 rad, times 2/pi is 0.159795, so K = 1.15980.The panel shows three decimals, so the check cannot be tighter.
Hand computation
1.16
1.16
0 %±0.1 %
A stripline’s effective permittivity is its dielectric constantA stripline sits in one uniform dielectric, so it is a TEM line and its effective permittivity equals the dielectric constant exactly: 4.3 in, 4.3 out. Any other value would be wrong.
Hand computation
4.3
4.3
0 %to the last figure
Dielectric loss of 8 inches of stripline at 2.5 GHza = pi f sqrt(e_eff) tand / c0 in Np/m, times 8.685889638 for dB/m. A stripline has e_eff exactly 4.3, so nothing here is fitted: pi x 2.5e9 x 2.07364414 x 0.02 / 299792458 x 8.685889638 = 9.43729887 dB/m, and 8 inches gives 1.91765913 dB.
Hand computation
1.91766
1.91766
< 0.001 %to the last figure
Against the 2.31 dB rule of thumb for dielectric lossRule of thumb: loss = 2.31 dB per inch x f in GHz x tand x sqrt(e_eff). Here 2.31 x 2.5 x 0.02 x 2.073644 x 8 inches = 1.9160 dB, within a tenth of a per cent of the computed 1.9177 dB. The gap is the rounding in 2.31: the exact coefficient is 2.3119.The rule is quoted to three figures, so a tighter band would test its rounding, not the physics.
AccuracyExact for ideal parts. On a real board the capacitor is the main uncertainty: a class 2 ceramic loses much of its value under DC bias and over temperature, which moves the corner.
Case
Kind of evidence
Expected
Computed
Difference
Cut-off of 10 k and 100 nFf = 1/(2 pi R C): 1/(2 pi x 10000 x 1e-7) = 159.1549431 Hz.
Resonance of 10 µH with 22 µFf = 1/(2 pi sqrt(LC)): sqrt(2.2e-10) = 1.4832397e-5, times 2 pi is 9.3194699e-5, reciprocal 10730.22 Hz.
Hand computation
10730.2
10730.2
< 0.001 %±0.001 %
Characteristic impedance of the same pairZ = sqrt(L/C): sqrt(10/22) = sqrt(0.4545454545) = 0.6741999 Ω.
Hand computation
0.6742
0.6742
< 0.001 %to the last figure
The capacitor that tunes 10 µH to 10 kHzC = 1/(L (2 pi f)^2): 2 pi x 10000 = 62831.853, squared is 3.9478418e9, times 1e-5 is 39478.418, reciprocal 2.5330296e-5 F.
AccuracyA lumped model: N identical capacitors, each C, ESR and ESL in series. It ignores the plane pair, so it holds only below the first plane resonance.
Case
Kind of evidence
Expected
Computed
Difference
Target impedance for 3 % of 3.3 V under a 0.5 A stepZ = dV/dI, with dV the allowed deviation: 3.3 x 0.03 = 0.099 V over 0.5 A = 0.198 Ω exactly.
Hand computation
0.198
0.198
< 0.001 %to the last figure
Self-resonance of 100 nF with 1.2 nH of loop inductancef = 1/(2 pi sqrt(L C)): sqrt(1.2e-16) = 1.0954451e-8, times 2 pi is 6.8828847e-8, reciprocal 14.5288 MHz.
One LSB of a 12-bit converter on a 3.3 V referenceLSB = V_FS/2^N: 3.3/4096 = 0.0008056640625 V exactly.
Hand computation
0.000805664
0.000805664
0 %to the last figure
The ideal signal-to-noise ratio of 12 bitsIdeal SNR = 6.02 N + 1.76 dB, from quantisation noise: 74 dB for 12 bits, the figure every data-conversion text gives.The panel shows one decimal, so the check cannot be tighter.
Load capacitors for a 12 pF crystal with 3 pF of strayThe two capacitors are in series across the crystal, so C_L = C/2 + C_stray and C = 2(C_L - C_stray): 2 x (12 - 3) = 18 pF, an E24 value.
Hand computation
1.8e-11
1.8e-11
0 %to the last figure
The load the crystal then seesTwo 18 pF in series is 9 pF. Add the 3 pF stray and the crystal sees 12 pF, its specified load.
Hand computation
1.2e-11
1.2e-11
0 %to the last figure
Checked against a stored result (11)
These follow a documented method, and most cite it.