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Full changelogEngine 1.18.3

LDO Dissipation & Limits

Power & Regulators

Dissipation, junction temperature and the real thermal current limit of a linear regulator.

Inputs

Board profile

Fills Ambient temperature and Junction temperature limit from your board profile.

V
V
A
250 mA
A
50 µA
V
°C
SOT-23 ≈ 250, SOT-223 ≈ 60 (with copper), DPAK ≈ 50, SOIC-8 ≈ 120
°C/W
°C
°C

Results

1 passed
Dissipation PD

(1.7 V × 250 mA) + quiescent
425.3mW
Pass

Checked: PD ≤ 833 mW, which holds TJ to 105 °C (RθJA 60.0 °C/W, TA 55 °C), and Vin − Vout ≥ the 300 mV dropout
Show working
  1. DissipationP = (V_in − V_out) × I_out + V_in × I_Q = (5 − 3.3) × 0.25 + 5 × 0.00005 = 425.3 mW
  2. Junction temperatureT_J = T_A + P × R_θJA = 55 + 425 mW × 60.0 °C/W = 80.5 °C
  3. Thermal current limitI_max = ((T_lim − T_A) / R_θJA − V_in × I_Q) / (V_in − V_out) = ((105 − 55) / 60.0 − 5 × 0.00005) / 1.7 = 490 mA
Junction temperature TJ

TA + 25.5 °C rise
80.5°C
RθJA you need

this package is enough
117.6°C/W
All results (3)
Efficiency

≈ Vout/Vin
66.0%
Thermal current limit Imax

for TJ ≤ 105 °C at TA = 55 °C
490mA
Max dissipation allowed
833.3mW
TJ = 81 °C, 24 °C below your design limit. The thermal limit is 490 mA.
TJ vs Iout

Accuracy

Source
  • JEDEC JESD51-2

JEDEC JESD51-2, Integrated Circuits Thermal Test Method, still air the equation

Precision
The dissipation is exact arithmetic.

Junction temperature and the current limit are only as good as R_thetaJA, which depends on the board as much as the package.

Most of the uncertainty comes from Package thermal resistance. Tighten that first.

Verified against

1 independent case. See the working.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Circuit

The principle

A linear regulator is a controlled resistor in series with the load. It drops the voltage difference at the full load current, so the loss is a voltage difference times a current, not a percentage. The package must carry that heat away.

Dissipation
PD=(Vin−Vout) Iout+VinIQP_D = (V_{in} - V_{out})\,I_{out} + V_{in} I_{Q}
The quiescent term dominates in sleep, when Iout is microamps.
Efficiency
η=VoutIoutVin(Iout+IQ)≈VoutVin\eta = \frac{V_{out} I_{out}}{V_{in}(I_{out}+I_Q)} \approx \frac{V_{out}}{V_{in}}
Junction temperature
TJ=TA+PD RθJAT_J = T_A + P_D\,R_{θJA}
Thermal current limit
Imax=TJ(max)−TARθJA−VinIQVin−VoutI_{max} = \frac{\dfrac{T_{J(max)} - T_A}{R_{θJA}} - V_{in} I_Q}{V_{in} - V_{out}}
In a real enclosure this, not the datasheet current rating, is usually the limit.
Dropout condition
Vin−Vout  ≥  VDO(Iout, T)V_{in} - V_{out} \;\geq\; V_{DO}(I_{out},\,T)
  • VDOV_{DO}dropout voltage; rises with load current and temperature
  • IQI_Qquiescent current to ground; it does not reach the load
  • RθJAR_{θJA}junction-to-ambient thermal resistance as mounted
More detail

What to check

  • Dropout at your full current and temperature extremes. A "300 mV" LDO may need 600 mV at full load and −40 °C.
  • RθJA as mounted. Datasheet values come from a standard JEDEC test board. Your copper can make it much better or much worse.
  • Stability. Keep the output capacitor inside the datasheet's ESR and capacitance region, after DC-bias derating. Older LDOs need a minimum ESR and can oscillate on ceramics.
Rule of thumb. Above about 0.5 W, consider a buck upstream. Use an LDO for quiet, not efficiency: a good one rejects 60–80 dB of supply ripple at low frequency, less at high frequency and near dropout.
Related: Junction Temperature & Safe Limits for the Rθ network, Copper Area & Thermal Vias for improving RθJA.

Engine version ⁨1.18.3⁩