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Full changelogEngine 1.18.3

Crystal Load Capacitance

Signal & Timing

Load capacitors for a crystal's specified CL, and the frequency error of the pair you fit.

Inputs

From the crystal datasheet; 8, 10, 12, 18 and 20 pF are common
Pins, pads and traces to ground; typically 2–5 pF
Hz
16 MHz
Your frequency budget for load error alone. USB full speed allows ±2500 ppm in total.
ppm
From the datasheet; 3–30 fF for AT-cut, 2–3 fF for a 32 kHz tuning fork
From the datasheet; 1–7 pF

Results

1 passed · 1 to check
Load capacitors, each C1=C2

ideal 18 pF · nearest E24
18pF
Pass

Checked: load error ≤ your 20 ppm budget. Rounding 18 pF to the nearest E24 value leaves +0.0 ppm, with 3 pF of stray.
Actual load capacitance CL

specified 12 pF · 25 % is stray
12pF
Frequency error

+0 Hz at 16 MHz
+0.0ppm
Trim sensitivity

frequency shift per picofarad of load
33.3ppm/pF
All results (1)
Series capacitance of the pair

without the stray
9pF
The crystal sees 12 pF against a specified 12 pF: +0.0 ppm, inside the 20 ppm budget.
Trim sensitivity is 33.3 ppm/pF, so 2 pF of stray error alone uses the whole budget. Measure the frequency on the first boards and adjust the pair.

The crystal sees the two capacitors in series, plus the stray. So in an equal pair, each capacitor is 2 × (CL − Cs), not CL.

error against the specified CL

Accuracy

Verified against

2 independent cases. See the working.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Parts that track move together.Inputs in the same group move together, like a matched pair or parts from one reel. Leave independent parts ungrouped: that is the safe choice.

Circuit

The principle

A crystal is calibrated to run at its nominal frequency with a specific load capacitance CL across its terminals. In a Pierce oscillator, as in most microcontrollers, that load is two capacitors to ground plus the stray from pins and traces. Get the pair wrong and the crystal runs at a steady offset.

What the crystal sees
CL=C1C2C1+C2+CsC_L = \frac{C_1 C_2}{C_1 + C_2} + C_s
C1 and C2 are in series across the crystal; the stray adds in parallel.
Equal pair for a given C_L
C1=C2=2 (CL−Cs)C_1 = C_2 = 2\,(C_L - C_s)
Load resonance
fL=fs(1+Cm2 (C0+CL))f_L = f_s\left(1 + \frac{C_m}{2\,(C_0 + C_L)}\right)
The crystal runs above its series resonance fs by an amount set by the load. Cm and C0 are on the datasheet.
Error from a wrong load
Δff=Cm2(1C0+CL′−1C0+CL)\frac{\Delta f}{f} = \frac{C_m}{2}\left(\frac{1}{C_0 + C_L^{\prime}} - \frac{1}{C_0 + C_L}\right)
CL is the specified load, CL′ what your board presents. More load, lower frequency.
Trim sensitivity
S=Cm2 (C0+CL)2S = \frac{C_m}{2\,(C_0 + C_L)^{2}}
Frequency shift per unit of load capacitance. A small CL and C0 make a crystal easy to pull, and easy to get wrong.
  • CLC_Lload capacitance the crystal is specified for
  • CsC_sstray capacitance of pins, pads and traces, to ground
  • C1,C2C_1, C_2the two load capacitors, crystal terminal to ground
  • CmC_mmotional capacitance of the crystal
  • C0C_0shunt capacitance of the crystal
  • fsf_sseries resonance
More detail

Estimating the stray

Each oscillator pin adds a few picofarads, and a trace over a ground plane adds roughly 1 pF per centimetre. Two to five picofarads in total is usual on a compact layout. The trim sensitivity shows what each unmeasured picofarad costs in ppm.

Measure, then trim. On the first boards, measure the frequency with a counter (or a timer output derived from it) and adjust the pair. 22 pF capacitors on a 12 pF crystal is a common mistake: it shows up as a clock that loses seconds a day, or a UART that works with only some hosts.

Not covered here

  • Gain margin. Whether the oscillator can start the crystal at this load is a separate check: the negative-resistance test in the vendor's application note. Larger load capacitors need more gain and slow the start-up.
  • Drive level. The power in the crystal must stay within its rating; a series resistor on the output side is the usual control.
  • Temperature and ageing. Both add to the load error. The budget you enter is the share for load error alone.

32.768 kHz crystals

Tuning-fork crystals are less sensitive per picofarad, but their budget is tighter: 20 ppm is 1.7 s per day. Low-CL parts (6–7 pF) are common, so the stray is a large share of the total.

12 pF crystal, 3 pF stray
Each capacitor should be 2 × (12 − 3) = 18 pF, an E24 value. The crystal sees 9 + 3 = 12 pF and runs on frequency.
The same crystal with a 22 pF pair
The crystal sees 11 + 3 = 14 pF, 2 pF high. With C_m = 15 fF and C_0 = 3 pF the error is −59 ppm: a 16 MHz clock 940 Hz low, or an RTC that loses 5 s per day.
References: STMicroelectronics AN2867, Oscillator design guide for STM8 and STM32 microcontrollers (load capacitors and gain margin). Microchip AN826, Crystal Oscillator Basics and Crystal Selection. IEC 60444-1 (equivalent-circuit parameters). Related: RC / RL Filter & Time Constant, for the low-pass formed by the series resistor and C2.

Engine version ⁨1.18.3⁩