RobustPCBWhere Robust Design Starts
CalculatorsالعربيةUpgradeSign inSign up

What's new

Full changelogEngine 1.18.3

Buck Converter Design

Power & Regulators

Inductor and output capacitor for a synchronous buck, with the current waveform.

Inputs

V
V
A
Hz
500 kHz
H
10 µH
ΔIL as % of Iout. 20–40 % is typical.
%
F
44 µF
Ω
5 mΩ
%

Results

1 passed
Suggested L for 30 % ripple
8.861µH
Pass

Checked: your 10 µH inductor against the 8.861 µH needed for 30 % ripple at 2 A
Show working
  1. Duty cycleD = V_out / (V_in × η) = 3.3 / (12 × 0.9) = 30.6 %
  2. Inductor ripple currentΔI_L = (V_in − V_out) × D / (L × f_sw) = 8.7 × 0.3056 / (10 µH × 500 kHz) = 531.7 mA
  3. Inductor for 30 % rippleL = (V_in − V_out) × D / (f_sw × I_out × 0.3) = 8.7 × 0.3056 / (500 kHz × 2 × 0.3) = 8.861 µH
  4. Peak inductor currentI_pk = I_out + ΔI_L / 2 = 2 + 532 mA / 2 = 2.266 A
Inductor ripple ΔIL

27 % of Iout
531.7mA
Peak inductor current Ipk

saturation rating ≥ 2.719 A
2.266A
Output ripple ΔVout

C 3 mV + ESR 2.7 mV
5.679mV
All results (6)
Duty cycle D

ideal 27.5 %, on-time 611 ns
30.6%
Inductor RMS current
2.006A
Average input current Iin
611.1mA
Cin RMS current
921.3mA
DCM boundary

below this load, IL reaches zero
265.8mA
Loss at this efficiency
733.3mW
Ripple ratio 27 % meets your 30 % target.

Choose an inductor with saturation current above 2.719 A (peak + 20 %, at temperature) and RMS rating above 2.006 A.

Input capacitor RMS current: 921.3 mA. Place the input ceramics closest to the IC's VIN and PGND pins.

iL(t)

Accuracy

Precision
Ideal-switch relations, exact for the assumed waveform.

They ignore dead time, switch drops and the inductance lost near saturation, so expect more ripple than this and check the inductor curve at your peak current.

Most of the uncertainty comes from Inductor. Tighten that first.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Circuit

The principle

A buck converter switches one end of an inductor between Vin and ground. In steady state the inductor's volt-seconds balance over each cycle, and that gives the duty cycle, the ripple and the component ratings.

Volt-second balance → duty cycle
(Vin−Vout) ton=Vout toff  ⇒  D=VoutVin(V_{in}-V_{out})\,t_{on} = V_{out}\,t_{off} \;\Rightarrow\; D = \frac{V_{out}}{V_{in}}
With losses, D ≈ Vout /(η·Vin): a little more on-time makes up the loss.
Inductor ripple current
ΔIL=(Vin−Vout) DL fsw=Vout(1−D)L fsw\Delta I_L = \frac{(V_{in}-V_{out})\,D}{L\,f_{sw}} = \frac{V_{out}(1-D)}{L\,f_{sw}}
Inductor selection for a target ripple ratio r
L=(Vin−Vout) Dfsw r IoutL = \frac{(V_{in}-V_{out})\,D}{f_{sw}\, r\, I_{out}}
r = ΔIL / Iout. r ≈ 0.3 balances inductor size, RMS loss and transient response.
Peak and RMS inductor current
Ipk=Iout+ΔIL2IL,rms=Iout2+ΔIL212I_{pk} = I_{out} + \frac{\Delta I_L}{2} \qquad I_{L,rms} = \sqrt{I_{out}^{2} + \frac{\Delta I_L^{2}}{12}}
Output voltage ripple
ΔVout=ΔIL8 Cout fsw+ΔIL⋅ESR\Delta V_{out} = \frac{\Delta I_L}{8\,C_{out}\,f_{sw}} + \Delta I_L \cdot ESR
Capacitive term plus ESR term. Ceramics: the first dominates. Electrolytics and polymers: usually the ESR term.
Input capacitor RMS current
ICin,rms=IoutD(1−D)I_{C_{in},rms} = I_{out}\sqrt{D(1-D)}
Largest at D = 0.5, where it is Iout/2. It sets input capacitor heating and life.
CCM / DCM boundary
Iout,crit=ΔIL2I_{out,crit} = \frac{\Delta I_L}{2}
  • DDduty cycle of the high-side switch
  • ΔIL\Delta I_Lpeak-to-peak inductor ripple current
  • fswf_{sw}switching frequency
  • ESRESRequivalent series resistance of the whole output capacitor bank
  • η\etaefficiency at this operating point
More detail

Switching frequency

Higher fsw shrinks L and C, but switching and gate-drive loss rise in proportion and EMI gets harder to control. 300–600 kHz is common for general power and 1–2 MHz where size matters. Automotive designs often run near 2.2 MHz to stay clear of the AM broadcast band (up to about 1.7 MHz).

Layout

The hot loop. Input capacitor → high-side FET → low-side FET → back to the capacitor. Its area sets radiated EMI and switch-node ringing: make it as small as possible, on one layer, over an unbroken plane.
  • Keep the switch node copper small.
  • Route the feedback trace away from the switch node and inductor, referenced to the output capacitor's ground.
  • Use the capacitance left after DC-bias derating: a 22 µF X5R 0805 rated 6.3 V can be under 10 µF at 5 V.

Transient response. A load step ΔI dips the output by roughly ΔI·tresponse/Cout, with tresponse set by the loop bandwidth. To reduce the dip, add capacitance or bandwidth, not inductance.

Related: MOSFET Loss Budget for the switch, Decoupling & Bulk Capacitance for the load side, Trace Width for the power path.

Engine version ⁨1.18.3⁩