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Full changelogEngine 1.18.3

MOSFET Loss Budget

Power & Regulators

Switching MOSFET losses split four ways, and the junction temperature they cause.

Inputs

Board profile

Fills Ambient temperature from your board profile.

V
The current during conduction, not the cycle average
A
%
Ω
20 mΩ
Silicon: about ×1.5 at 100 °C, ×1.8 at 125 °C
Hz
100 kHz
s
40 ns
s
40 ns
C
30 nC
V
Co(er) from the datasheet, not the small-signal value
F
300 pF
°C
°C/W
Your part's rating minus margin. Silicon MOSFETs are usually rated 150 °C or 175 °C.
°C

Results

1 passed
Total in the FET
1.37W
Pass

Checked: Ptotal ≤ 1.6 W, which holds TJ to 125 °C (RθJA 50.0 °C/W, TA 45 °C)
Conduction loss
375mW
Switching loss
960mW
Junction temperature
113.5°C
All results (3)
Coss loss
34.56mW
Gate-drive power

dissipated in the driver
30mW
Effective RDS(on) hot
30mΩ
TJ = 113 °C at 45 °C ambient: 12 °C below your 125 °C limit.

Gate-drive loss 30 mW is dissipated in the driver and gate resistor, not in the MOSFET.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Waveform

The principle

A switching MOSFET loses power four ways, and they scale differently. Conduction loss grows with current squared and duty; switching loss with voltage × current × frequency. So the same part can suit 20 kHz and be a poor choice at 500 kHz.

Conduction
Pcond=ID2 RDS(on)(TJ) DP_{cond} = I_{D}^{2}\, R_{DS(on)}(T_J)\, D
Use the hot RDS(on): for silicon, about ×1.5 at 100 °C and ×1.8 at 125 °C. Iterate, since the loss raises TJ.
Switching (hard-switched)
Psw=12VDSID(tr+tf) fswP_{sw} = \tfrac{1}{2} V_{DS} I_{D} (t_r + t_f)\, f_{sw}
The overlap of voltage and current in each transition. Gate-drive strength and layout inductance set tr and tf.
Gate drive
Pgate=QgVGSfswP_{gate} = Q_g V_{GS} f_{sw}
Dissipated in the driver and gate resistor, not in the MOSFET.
Output capacitance
PCoss=12CossVDS2fswP_{C_{oss}} = \tfrac{1}{2} C_{oss} V_{DS}^{2} f_{sw}
The energy in Coss is dumped into the channel at each hard turn-on. It matters at high voltage and frequency.
Junction temperature
TJ=TA+(Pcond+Psw+PCoss) RθJAT_J = T_A + (P_{cond}+P_{sw}+P_{C_{oss}})\,R_{θJA}
  • RDS(on)R_{DS(on)}on-resistance at the actual junction temperature
  • tr, tft_r,\,t_ftransition times, set by gate drive and Qgd
  • QgQ_gtotal gate charge at the drive voltage used
  • CossC_{oss}output capacitance: the energy-related Co(er), not the small-signal value
More detail

Choosing the part

Lower RDS(on) usually brings more Qg and Coss: half the RDS(on) typically means about twice the Qg. Choose the lowest total loss at your frequency, not the lowest RDS(on).

Practical checks

  • Gate drive voltage. A logic-level FET at 4.5 V may have double its 10 V RDS(on). Read the RDS(on) vs VGS curve.
  • Gate resistor trades EMI against switching loss: 10 Ω instead of 2 Ω can double Psw.
  • Reverse recovery (Qrr) adds loss in hard-switched bridges, often more than the Coss term at high voltage.
  • Half-bridges. Add a gate pull-down close to the pin to stop dV/dt-induced turn-on.
Related: Junction Temperature & Safe Limits for the thermal path; Buck Converter Design for the currents to feed in here.

Engine version ⁨1.18.3⁩