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Full changelogEngine 1.18.3

PDN Target Impedance

Power & Regulators

Impedance of a real capacitor bank against its target, and the frequency above which more capacitors stop helping.

Inputs

Board profile

Fills Dielectric constant between the planes from your board profile.

V
%
A
A spot frequency, for comparison with a simulation
Hz
1 MHz
Pad, vias and loop to the plane, added to each part's ESL. Drawn as the dashed typical curve.
H
800 pH
The verdict and headline results use this value
H
2 nH
From the part's DC-bias curve at your rail voltage. Small case sizes can lose more than half.
%
Used only for the two-via lower bound; it does not change the verdict
Sets the first cavity mode, above which this lumped model does not apply
Ω
2 mΩ
H
2 µH
Below it the real regulator impedance is lower than modelled, so the curve is conservative there
Hz
50 kHz
GroupCountC (F)ESR (Ω)Part ESL (H)Distance to load (m)
100 nF20 mΩ600 pH3 mm
4.7 µF8 mΩ1 nH12 mm
100 µF10 mΩ2.5 nH30 mm

Results

2 to check · 1 failed
Peak impedance in band |Z|pk
2.442Ω
Fail

Checked: peak |Z| ≤ Ztarget = 2.7 mΩ from 1 kHz to 72.29 MHz, at the worst-case 2 nH mounting inductance
Impedance at the stated frequency |Z|(f)

at 1 MHz
5.328mΩ
Highest frequency the board holds the target fmax
3.374MHz
Target impedance Ztarget
2.7mΩ
All results (6)
High-frequency inductance floor Lnode
127.4pH
First plane cavity mode fcav
722.9MHz
Plane pair capacitance Cpl

usually negligible unless this is a buried-capacitance core
1.904nF
Spreading inductance of the nearest group Lspread
59.91pH
Peak impedance at the typical mounting inductance

the optimistic case, for comparison
2.446Ω
Two-via loop inductance, lower bound

vias only. It leaves out the pad and capacitor terminals, often the larger part, so do not use it as the mounting inductance.
74.95pH
Peak impedance is 2.44 Ω at 9.441 kHz, above the 2.7 mΩ target. Add bulk capacitance, use bulk parts with enough ESR to damp it, or raise the regulator's loop bandwidth above this frequency. It is below the self-resonance of every group, so the bank is still capacitive and resonates with the regulator's own 2 µH output inductance. Mounting and placement will not move it.
Halving the ESR raises the peak from 2.44 Ω to 3.45 Ω: lower-ESR parts can make the peak worse. ESR damps the anti-resonance between groups.
No number of these parts holds the target above 3.374 MHz. Improve the mounting, move a group closer to the load, or rely on package and on-die capacitance. The bank's mounting and spreading inductance (127.4 pH) sets a floor that more parts do not lower.

This is the impedance at the capacitor pads. Above the package resonance the die sees package and on-die capacitance, which this model leaves out.

Ztarget = VDD × ripple ÷ ΔI = 2.7 mΩ. It is a heuristic that assumes a worst-case step with a flat current spectrum. Meeting it is necessary but does not guarantee the ripple specification.

The verdict covers 1 kHz to 72.29 MHz, a tenth of the first plane cavity mode (722.9 MHz). The factor of ten is a chosen margin, not a published limit: the plane stops acting as a lumped capacitor well before that mode.

The curve peaks higher, at 12 Ω near 319.9 MHz, but that value is a model artefact. The plane is modelled as a lossless capacitor; on a real board, plane loss sets how high it goes. Read the shape, not the value.

Below the 50 kHz loop bandwidth, the regulator's feedback gives a lower impedance than modelled, so the curve is conservative there.

Results use the worst-case mounting inductance, 2 nH. At the typical 800 pH the peak would be 2.45 Ω. Ordinary pads and vias span roughly 0.3 to 2 nH.

Each group as the plane sees it
GroupCountC after deratingGroup ESRGroup LSpreading LBranch resonance
Local 0402 100 nF201.2 µF1 mΩ190 pH59.9 pH10.5 MHz
Mid 0805 4.7 µF822.6 µF1 mΩ463 pH87.6 pH1.56 MHz
Bulk 100 µF polymer2120 µF5 mΩ2.36 nH106 pH299 kHz
Diminishing returns on the first group
Count in the first groupPeak |Z|f_max
202.44 Ω3.37 MHz
402.31 Ω4.55 MHz
802.08 Ω5.76 MHz
1602.56 Ω6.75 MHz
→ ∞—8.28 MHz
bank, worst-case mountbank, typical mountLocal 0402 100 nFMid 0805 4.7 µFBulk 100 µF polymer

Accuracy

Source
  • Smith et al. (1999)
  • Smith and Bogatin

Smith, Anderson, Forehand, Pelc and Roy, Power distribution system design methodology and capacitor selection for modern CMOS technology, IEEE Transactions on Advanced Packaging (1999) the equation

Smith and Bogatin, Principles of Power Integrity for PDN Design Simplified the equation

Valid range
  • Plane pair separation 0.005 mm to 2 mm

Plane pair separation The spreading-inductance formula assumes the plane separation is much smaller than the distance from each group to the load. Outside this range it does not apply.

Precision
A lumped network with exact arithmetic, so the error lies in the inductances you enter.

Mounting inductance spans roughly 0.3 to 2 nH for ordinary pads and vias and sets the answer above about 30 MHz, so the verdict uses the worst-case value.

Most of the uncertainty comes from Typical mounting inductance per part. Tighten that first.

Verified against

7 independent cases. See the working.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Parts that track move together.Inputs in the same group move together, like a matched pair or parts from one reel. Leave independent parts ungrouped: that is the safe choice.

Cross-section

The principle

A power distribution network is judged by its impedance seen from the load, across frequency, against a target: the allowed rail deviation divided by the current step. Each capacitor group sits behind its own mounting and spreading inductance. Between any two groups there is an anti-resonance that more of the same part will not remove.

Target impedance
Ztarget=VDD rΔIZ_{target} = \frac{V_{DD}\,r}{\Delta I}
One real capacitor
Zc(f)=Resr+j(2πfLc−12πfC),Lc=ESL+LmountZ_c(f) = R_{esr} + j\left(2\pi f L_c - \frac{1}{2\pi f C}\right), \qquad L_c = ESL + L_{mount}
N identical parts, inside one group only
Zg(f)=ResrN+j(2πfLcN−12πfNC)Z_g(f) = \frac{R_{esr}}{N} + j\left(\frac{2\pi f L_c}{N} - \frac{1}{2\pi f N C}\right)
Spreading inductance to a group at distance d
Lspread=μ0h2πln⁡drvL_{spread} = \frac{\mu_0 h}{2\pi}\ln\frac{d}{r_v}
The radial parallel-plate result. Valid while h is much smaller than d, and below the first cavity mode.
Plane pair capacitance
Cpl=ε0εrAhC_{pl} = \frac{\varepsilon_0 \varepsilon_r A}{h}
The node impedance
1Zpdn(f)=1Zvrm+∑i1Zg,i+j2πfLspread,i+j2πfCpl\frac{1}{Z_{pdn}(f)} = \frac{1}{Z_{vrm}} + \sum_i \frac{1}{Z_{g,i} + j 2\pi f L_{spread,i}} + j 2\pi f C_{pl}
The floor, and the frequency it imposes
Lnode=(∑i1Lc,i/Ni+Lspread,i)−1,fmax=Ztarget2πLnodeL_{node} = \left(\sum_i \frac{1}{L_{c,i}/N_i + L_{spread,i}}\right)^{-1}, \qquad f_{max} = \frac{Z_{target}}{2\pi L_{node}}
First plane cavity mode
fcav≈c02aεrf_{cav} \approx \frac{c_0}{2 a \sqrt{\varepsilon_r}}
  • ZtargetZ_{target}the impedance the rail deviation and the current step allow
  • LmountL_{mount}pad, via pair and the loop back to the plane, per part
  • LspreadL_{spread}inductance of the radial path from a group to the load
  • LnodeL_{node}all the branch inductances in parallel: the high-frequency floor
  • fmaxf_{max}the frequency at which that floor reaches the target
  • fcavf_{cav}first plane cavity mode; the lumped model does not apply above it
  • CplC_{pl}capacitance of the plane pair itself
  • rvr_vvia barrel radius, the inner limit of the radial spread
More detail

When to stop adding capacitors

A 5 mΩ target with a 50 pH floor gives fmax = 15.9 MHz. Above fmax, only package and on-die capacitance help. The diminishing-returns table shows where more parts stop paying.

N in parallel applies only within a group

N parts divide R and L and multiply C only when they share a mount and a distance. Groups at different distances see different spreading inductance, which is why an anti-resonance appears between them.

Not modelled

Mutual inductance between adjacent mounts, and ESR change with frequency and temperature. DC-bias derating is the factor you enter from the part's own curve.

The plane pair appears as both a capacitance and a spreading inductance, which holds only well below the first cavity mode. Confirm with a two-port shunt-through VNA measurement; where it disagrees, trust the measurement.
Method: target impedance from Smith, Anderson, Forehand, Pelc and Roy (1999); spreading and plane results after Smith and Bogatin.

Engine version ⁨1.18.3⁩