Transient Thermal Impedance
Peak junction temperature under one pulse or a pulse train, from the datasheet R and tau set.
هذه الصفحة غير مترجمة بالكامل بعد. الأجزاء غير المترجمة معروضة بالإنجليزية.
المدخلات
ملف اللوحةFills Case or reference temperature وJunction temperature limit from your board profile.
| R (°C/W) | tau (s) | حذف الصف |
|---|---|---|
| 100 µs | ||
| 2 ms | ||
| 30 ms | ||
النتائج
المعيار: TJ ≤ 150 °C, with the reference node at 80 °C
كل النتائج (5)
sum of the R column
P × D × Rth
Zth has a log-log slope of 0.70 at the pulse width. While the heat is still in the die, one-dimensional flow gives a slope of about 0.5. A set far from that at early times is missing its fast stages or was badly digitised.
A Foster ladder matches only the measured terminal behaviour. Its internal nodes are not physical temperatures, so R2 is not the die attach. Two Foster ladders cannot be chained: adding a heat-sink Zth to a device Zth,JC is not valid.
إلى أي حد نعرف هذا الرقم
- JESD51-14
- JESD51-1
JESD51-14, Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction to Case of Semiconductor Devices with a Single Heat Flow Path المعادلة
JESD51-1, Integrated Circuit Thermal Measurement Method, Electrical Test Method المعادلة
- Pulse width at least 1e-9 s
Pulse width No published R and tau set resolves times below a nanosecond, so the ladder would be extrapolating.
The error is in the R and tau set and how it was measured: a junction-to-case set assumes an isothermal case, a junction-to-ambient set the JEDEC test board in still air.
عملياً يهيمن على عدم اليقين مدخل واحد: Foster stages. ضيّقه يضِق معه الجواب.
4 حالات في هذا الموقع تقارن هذه الحاسبة بأرقام حُسبت من دون كودها. اطّلع على الحساب.
هذه أداة مساعدة للتصميم. يبقى المهندس مسؤولاً عن التصميم وعن قراءة المرجع القياسي نفسه حيث يهم ذلك.
المسح البارامتري
غيّر مدخلاً واحداً على مدى، وشاهد الإجابة والحكم والهامش عند كل خطوة، جدولاً ومنحنى.Proأسوأ الحالات
أضف التفاوتات إلى المدخلات لتحصل على النطاق المضمون حول الإجابة الاسمية، لا الحالة النموذجية وحدها.Proأعطِ مدخلاً واحداً على الأقل تفاوتاً أكبر من صفر.
Waveform
المبدأ
A steady-state thermal resistance assumes the power runs for ever. Under a short pulse, the heat capacity of the silicon limits the rise instead, and the transient thermal impedance Zth(t) describes it. At 100 W, 1 °C/W steady state means a 100 °C rise; a 100 µs pulse into 0.02 °C/W means 2 °C.
- thermal resistance of one Foster stage, in °C/W
- its time constant, Ri Ci, in seconds
- transient thermal impedance: rise per watt after a step of that duration
- pulse width
- period of the train
- duty, tp over T
- junction temperature
- the node the set was measured against
تفاصيل إضافية
What a Foster ladder is not
Its elements have no physical location: R2 is not the die attach. The ladder is a fit to the measured terminal response, so two cannot be put in series. The standard route to chaining is the Cauer form, and that conversion is numerically fragile beyond three or four stages.
What superposition assumes
- Linearity. Silicon conducts heat less well when hot, so a curve measured cool understates a hot design.
- The same heated area. A device in linear mode concentrates power in a smaller area, so its real Zth is higher.
- One source. No heating from neighbouring dies.
- The measured boundary. Below about 1 ms, junction-to-case and junction-to-ambient curves coincide. Above about 1 s, a junction-to-ambient curve describes the JEDEC test board in still air, not yours.
Not covered
إصدار المحرك 1.18.3