ما الجديد

Transient Thermal Impedance

Thermal

Peak junction temperature under one pulse or a pulse train, from the datasheet R and tau set.

هذه الصفحة غير مترجمة بالكامل بعد. الأجزاء غير المترجمة معروضة بالإنجليزية.

المدخلات

ملف اللوحة

Fills Case or reference temperature وJunction temperature limit from your board profile.

W
s
100 µs
The case for a junction-to-case set; the ambient for a junction-to-ambient set
°C
°C
R (°C/W)tau (s)حذف الصف
100 µs
2 ms
30 ms

النتائج

1 ناجحة · 1 للمراجعة
Peak junction temperature TJ
81.77°C
ناجح

المعيار: TJ ≤ 150 °C, with the reference node at 80 °C

Transient thermal impedance at the pulse width Zth(tp)
0.01766°C/W
Peak temperature rise ΔTJ
1.766°C
كل النتائج (5)
Steady-state thermal resistance Rth

sum of the R column

1°C/W
DC-equivalent rise

P × D × Rth

100°C
Energy per pulse
10mJ
Time to 63 % of Rth
244.7ms
Log-log slope of Zth at the pulse width
0.70
Peak junction temperature is 81.8 °C, 68.2 °C below the limit.
A Zth measured near room temperature understates the rise in a hot design. Superposition assumes linearity, and silicon conducts heat less well when hot. By how much depends on the package.

Zth has a log-log slope of 0.70 at the pulse width. While the heat is still in the die, one-dimensional flow gives a slope of about 0.5. A set far from that at early times is missing its fast stages or was badly digitised.

A Foster ladder matches only the measured terminal behaviour. Its internal nodes are not physical temperatures, so R2 is not the die attach. Two Foster ladders cannot be chained: adding a heat-sink Zth to a device Zth,JC is not valid.

single pulseD = 0.01D = 0.1D = 0.5

إلى أي حد نعرف هذا الرقم

من أين تأتي الطريقة
  • JESD51-14
  • JESD51-1

JESD51-14, Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction to Case of Semiconductor Devices with a Single Heat Flow Path المعادلة

JESD51-1, Integrated Circuit Thermal Measurement Method, Electrical Test Method المعادلة

صادقة ضمن
  • Pulse width at least 1e-9 s

Pulse width No published R and tau set resolves times below a nanosecond, so the ladder would be extrapolating.

مدى دقتها
Exact closed-form arithmetic, with nothing fitted.

The error is in the R and tau set and how it was measured: a junction-to-case set assumes an isothermal case, a junction-to-ambient set the JEDEC test board in still air.

عملياً يهيمن على عدم اليقين مدخل واحد: Foster stages. ضيّقه يضِق معه الجواب.

يُقاس مقابل

4 حالات في هذا الموقع تقارن هذه الحاسبة بأرقام حُسبت من دون كودها. اطّلع على الحساب.

هذه أداة مساعدة للتصميم. يبقى المهندس مسؤولاً عن التصميم وعن قراءة المرجع القياسي نفسه حيث يهم ذلك.

المسح البارامتري

غيّر مدخلاً واحداً على مدى، وشاهد الإجابة والحكم والهامش عند كل خطوة، جدولاً ومنحنى.Pro

أسوأ الحالات

أضف التفاوتات إلى المدخلات لتحصل على النطاق المضمون حول الإجابة الاسمية، لا الحالة النموذجية وحدها.Pro

أعطِ مدخلاً واحداً على الأقل تفاوتاً أكبر من صفر.

Waveform

المبدأ

A steady-state thermal resistance assumes the power runs for ever. Under a short pulse, the heat capacity of the silicon limits the rise instead, and the transient thermal impedance Zth(t) describes it. At 100 W, 1 °C/W steady state means a 100 °C rise; a 100 µs pulse into 0.02 °C/W means 2 °C.

Step response of a Foster ladder
Zth(t)=∑iRi(1−e−t/τi),τi=RiCiZ_{th}(t) = \sum_i R_i \left(1 - e^{-t/\tau_i}\right), \qquad \tau_i = R_i C_i
Steady-state thermal resistance
Rth=∑iRiR_{th} = \sum_i R_i
Temperature at the end of the n-th pulse
ΔT(n)=P∑iRi(1−e−tp/τi)(1−e−nT/τi)1−e−T/τi\Delta T(n) = P \sum_i R_i \frac{\left(1-e^{-t_p/\tau_i}\right)\left(1-e^{-nT/\tau_i}\right)}{1-e^{-T/\tau_i}}
Superposition of step responses, from a cold start.
Repetitive impedance in the steady state
Zth(tp,D)=∑iRi1−e−tp/τi1−e−T/τi,D=tpTZ_{th}(t_p, D) = \sum_i R_i \frac{1-e^{-t_p/\tau_i}}{1-e^{-T/\tau_i}}, \qquad D = \frac{t_p}{T}
As D → 1 it gives Rth; as T → ∞, the single-pulse Zth(tp); for a vanishing pulse at fixed D, D·Rth.
Valley, at the end of the off time
ΔTvalley=P∑i[Ri1−e−tp/τi1−e−T/τi]e−toff/τi\Delta T_{valley} = P \sum_i \left[ R_i \frac{1-e^{-t_p/\tau_i}}{1-e^{-T/\tau_i}} \right] e^{-t_{off}/\tau_i}
Common approximation, not used here
Zth(tp,D)≈D Rth+(1−D) Zth(tp)Z_{th}(t_p,D) \approx D\,R_{th} + (1-D)\,Z_{th}(t_p)
Correct at all three limits, wrong in between.
Early-time behaviour of a real device
Zth(t)=2AtπkρcZ_{th}(t) = \frac{2}{A}\sqrt{\frac{t}{\pi k \rho c}}
One-dimensional, constant heat flux into a thick solid: a slope of ½ on log-log axes, until the heat reaches the back of the die.
  • RiR_ithermal resistance of one Foster stage, in °C/W
  • τi\tau_iits time constant, Ri Ci, in seconds
  • ZthZ_{th}transient thermal impedance: rise per watt after a step of that duration
  • tpt_ppulse width
  • TTperiod of the train
  • DDduty, tp over T
  • TJT_Jjunction temperature
  • TrefT_{ref}the node the set was measured against
تفاصيل إضافية

What a Foster ladder is not

Its elements have no physical location: R2 is not the die attach. The ladder is a fit to the measured terminal response, so two cannot be put in series. The standard route to chaining is the Cauer form, and that conversion is numerically fragile beyond three or four stages.

What superposition assumes

  • Linearity. Silicon conducts heat less well when hot, so a curve measured cool understates a hot design.
  • The same heated area. A device in linear mode concentrates power in a smaller area, so its real Zth is higher.
  • One source. No heating from neighbouring dies.
  • The measured boundary. Below about 1 ms, junction-to-case and junction-to-ambient curves coincide. Above about 1 s, a junction-to-ambient curve describes the JEDEC test board in still air, not yours.

Not covered

Die-attach voids and ageing: Zth describes the new part. Electrothermal instability, so linear-mode safe operating area is not a Zth calculation. Second breakdown, dV/dt and dielectric failure. Lifetime: the peak-to-valley swing drives bond-wire and solder fatigue, but turning it into cycles to failure needs a model for your construction.
Method: JESD51-14 (transient dual-interface, junction to case) and JESD51-1 define how published R and tau sets are measured. JESD51-3, -5 and -7 define the boards for junction-to-ambient sets. Consult the standards themselves for anything that matters.

إصدار المحرك ⁨1.18.3⁩