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سجل التغييرات الكاملالمحرّك 1.18.3

RC / RL Filter & Time Constant

الإشارة والتوقيت

Cut-off, time constant, rise time and settling to n bits for a one-pole RC or RL filter.

هذه الصفحة غير مترجمة بالكامل بعد. الأجزاء غير المترجمة معروضة بالإنجليزية.

المدخلات

Ω
10 kΩ
F
100 nF
Hz
Hz
1 kHz

النتائج

1 للمراجعة
Cut-off frequency fc

بلا حكم: a corner frequency has no pass or fail. Where it belongs depends on the signals you keep and reject.

−3 dB point
159.2Hz
أظهر خطوات الحساب
  1. Cut-off frequencyf_c = 1 / (2π R C) = 1 / (2π × 10 kΩ × 100 nF) = 159.2 Hz
  2. Time constantτ = R × C = 10 kΩ × 100 nF = 1 ms
  3. Rise time, 10 to 90 %t_r = 2.2 × τ = 2.2 × 1 ms = 2.2 ms
Time constant τ

63.2 % of final value
1ms
Rise time (10–90 %)

tr = 2.2 τ = 0.35/fc
2.2ms
كل النتائج (5)
Capacitance C
100nF
Resistance R
10kΩ
Settling to 12 bits

9.0 time constants
9.01ms
Response at 1 kHz

×0.1572, phase -81.0°
-16.07dB
Noise bandwidth

ENBW = 1.57 · fc for one pole
250Hz
The output impedance reaches 10 kΩ. The next stage needs a much higher input impedance, or the cut-off moves.
low-pass

إلى أي حد نعرف هذا الرقم

مدى دقتها
Exact for ideal parts.

On a real board the capacitor is the main uncertainty: a class 2 ceramic loses much of its value under DC bias and over temperature, which moves the corner.

عملياً يهيمن على عدم اليقين مدخل واحد: Capacitance. ضيّقه يضِق معه الجواب.

يُقاس مقابل

حالة واحدة في هذا الموقع تقارن هذه الحاسبة برقم حُسب من دون كودها. اطّلع على الحساب.

هذه أداة مساعدة للتصميم. يبقى المهندس مسؤولاً عن التصميم وعن قراءة المرجع القياسي نفسه حيث يهم ذلك.

المسح البارامتري

غيّر مدخلاً واحداً على مدى، وشاهد الإجابة والحكم والهامش عند كل خطوة، جدولاً ومنحنى.Pro

أسوأ الحالات

أضف التفاوتات إلى المدخلات لتحصل على النطاق المضمون حول الإجابة الاسمية، لا الحالة النموذجية وحدها.Pro

Circuit

المبدأ

An RC or RL network is a divider whose ratio changes with frequency. The cut-off fc and the time constant τ are the same fact seen two ways: one sets the attenuation, the other how fast the output settles.

Cut-off frequency
fc=12πRC(RL: fc=R2πL)f_c = \frac{1}{2\pi R C} \qquad \t{(RL: } f_c = \frac{R}{2\pi L}\t{)}
Time constant
τ=RC=12πfc(RL: τ=L/R)\tau = R C = \frac{1}{2\pi f_c} \qquad \t{(RL: } \tau = L/R\t{)}
Low-pass magnitude and phase
∣H∣=11+(f/fc)2φ=−arctan⁡ ⁣(ffc)\left|H\right| = \frac{1}{\sqrt{1+(f/f_c)^{2}}} \qquad \varphi = -\arctan\!\left(\frac{f}{f_c}\right)
High-pass magnitude
∣H∣=f/fc1+(f/fc)2\left|H\right| = \frac{f/f_c}{\sqrt{1+(f/f_c)^{2}}}
Step response
v(t)=Vf(1−e−t/τ)v(t) = V_{f}\left(1 - e^{-t/\tau}\right)
Rise time
tr=2.2 τ=0.35fct_r = 2.2\,\tau = \frac{0.35}{f_c}
10 % to 90 % of the final value.
Settling to n-bit accuracy
tsettle=τln⁡ ⁣(2 n+1)≈0.69 (n+1) τt_{settle} = \tau \ln\!\left(2^{\,n+1}\right) \approx 0.69\,(n+1)\,\tau
12 bits needs about 9 time constants; 16 bits about 12.
Equivalent noise bandwidth
ENBW=π2fc=1.57 fcENBW = \frac{\pi}{2} f_c = 1.57\, f_c
Use this, not fc, to integrate noise through the filter.
  • fcf_c−3 dB cut-off, where |H| = 1/√2 and the phase is 45°
  • τ\tautime constant, 63.2 % of a step in one τ
  • ENBWENBWequivalent noise bandwidth of the single pole
تفاصيل إضافية

Choosing R and C

Only the product RC is fixed. A large R adds thermal noise and is sensitive to bias current and leakage. A small R loads the source. Typical ranges:

  • ADC anti-alias: 100 Ω to 1 kΩ, so the sampling capacitor can recharge.
  • Op-amp feedback and active filters: 1 kΩ to 100 kΩ.
  • Debounce and long timers: 10 kΩ to 1 MΩ, with a film or C0G capacitor. A firmware debounce is often simpler.

Use C0G/NP0 for filters and timing: it is stable and has no DC-bias effect. Use X7R only where a ±15 % shift plus DC-bias loss is acceptable. Never use Y5V in a signal path.

One RC is not enough anti-alias filtering above about 12 bits. A single pole falls at 20 dB/decade, so a signal at 10× fc is only 20 dB down. Oversample, or use a multi-pole active filter.

Cascading

Two identical sections do not make a clean two-pole filter. Buffered, the −3 dB point falls to 0.64 fc. Connected directly, the second section loads the first and it falls to about 0.37 fc. For a true two-pole response, design a Sallen-Key or MFB stage.

Related: ADC Resolution & Noise Budget, for acquisition settling.

إصدار المحرك ⁨1.18.3⁩