RobustPCBWhere Robust Design Starts
الحاسباتEnglishUpgradeتسجيل الدخولإنشاء حساب

ما الجديد

سجل التغييرات الكاملالمحرّك 1.18.3

Decoupling & Bulk Capacitance

الإشارة والتوقيت

How many capacitors hold a rail under its target impedance, and where each stops acting as a capacitor.

هذه الصفحة غير مترجمة بالكامل بعد. الأجزاء غير المترجمة معروضة بالإنجليزية.

المدخلات

V
%
A
s
2 ns
Hz
100 MHz
F
100 nF
0402: 0.5–0.9 nH package plus 0.3–1 nH of vias and pads; the vias usually dominate
H
1.2 nH
Ω
20 mΩ

النتائج

1 ناجحة · 2 للمراجعة
Capacitors required

to reach 100 MHz
4
ناجح

المعيار: 10 in the bank against the 4 needed to hold 198 mΩ up to 100 MHz
Target impedance Ztgt

99 mV allowed on 500 mA
198mΩ
Self-resonant frequency fSRF
14.53MHz
Suggested bulk capacitance

for the low-frequency end; electrolytic or polymer
4.019µF
كل النتائج (4)
Bank floor impedance

ESR/N at resonance
2mΩ
Total loop inductance

ESL/N
120pH
Charge-based minimum C

ΔI·tr/ΔV, for the step alone
10.1nF
Signal knee frequency

0.35 / tr
175MHz
Holding 198 mΩ at 100 MHz needs N ≥ 4 capacitors of 1.2 nH loop inductance each. You have 10.
Above 14.53 MHz each capacitor acts as an inductor. To go higher, cut the loop inductance: shorter traces, via-in-pad, the capacitor right at the pin. That is the self-resonant frequency. Above it the capacitance no longer matters; only the loop inductance does.
Check DC bias derating: a small X5R/X7R part can lose half its capacitance at 3.3 V. Use the manufacturer's bias curve.

Target impedance ΔV/ΔI = 198 mΩ. Keep the power network below it from DC to 100 MHz.

bank of 10target impedance

إلى أي حد نعرف هذا الرقم

مدى دقتها
A lumped model: N identical capacitors, each C, ESR and ESL in series.

It ignores the plane pair, so it holds only below the first plane resonance.

عملياً يهيمن على عدم اليقين مدخل واحد: Loop inductance, each. ضيّقه يضِق معه الجواب.

يُقاس مقابل

2 حالات في هذا الموقع تقارن هذه الحاسبة بأرقام حُسبت من دون كودها. اطّلع على الحساب.

هذه أداة مساعدة للتصميم. يبقى المهندس مسؤولاً عن التصميم وعن قراءة المرجع القياسي نفسه حيث يهم ذلك.

المسح البارامتري

غيّر مدخلاً واحداً على مدى، وشاهد الإجابة والحكم والهامش عند كل خطوة، جدولاً ومنحنى.Pro

أسوأ الحالات

أضف التفاوتات إلى المدخلات لتحصل على النطاق المضمون حول الإجابة الاسمية، لا الحالة النموذجية وحدها.Pro

Circuit

المبدأ

A decoupling capacitor supplies the fast part of a load step, so the regulator and its inductive path do not have to. Above its self-resonant frequency it acts as the loop inductance of the part, its pads and its vias. Decoupling design is therefore mostly inductance design.

Target impedance of the power network
Ztarget=ΔVallowedΔIstepZ_{target} = \frac{\Delta V_{allowed}}{\Delta I_{step}}
Keep the PDN below this from DC to the knee frequency of the fastest edge on the rail.
Impedance of one real capacitor
Z(f)=ESR2+(2πf ESL−12πfC)2Z(f) = \sqrt{ESR^{2} + \left(2\pi f\,ESL - \frac{1}{2\pi f C}\right)^{2}}
Self-resonant frequency
fSRF=12πLloopCf_{SRF} = \frac{1}{2\pi\sqrt{L_{loop} C}}
Capacitive below it, inductive above. A 100 nF with 1.2 nH resonates near 14 MHz.
N capacitors in parallel
Zmin=ESRN,Ltot=ESLN,N≥2πfmaxLloopZtargetZ_{min} = \frac{ESR}{N}, \qquad L_{tot} = \frac{ESL}{N}, \qquad N \geq \frac{2\pi f_{max} L_{loop}}{Z_{target}}
N parts divide both ESR and inductance by N. That is why many small capacitors beat one large one.
Charge required by a step
C≥ΔI⋅trΔVC \geq \frac{\Delta I \cdot t_{r}}{\Delta V}
Voltage dip across inductance
ΔV=L didt\Delta V = L\,\frac{di}{dt}
1 nH with 0.5 A in 2 ns is 250 mV. So via inductance, not capacitance, dominates.
  • ESLESLloop inductance of the capacitor plus its pads, traces and vias
  • ESRESRequivalent series resistance, sets the floor of the impedance curve
  • fkneef_{knee}0.35/tr, the highest frequency with significant energy in the edge
تفاصيل إضافية

What reduces inductance

  • A short loop. Capacitor pad, via, plane, via, IC pin: each millimetre adds roughly 0.3–1 nH. If the top side is crowded, place the capacitor on the back, directly under the pin.
  • Via-in-pad, or two vias per terminal, roughly halves the via inductance.
  • A thin power-to-ground dielectric. A 50 µm core between the VDD and GND planes is a very low-inductance capacitor, and it works above the frequencies where discrete parts stop.
  • Smaller cases have lower package inductance: 0402 < 0603 < 0805. Reverse-geometry (0306) parts are lower still.
The "100 nF + 1 nF + 100 pF" ladder helps less than people think. With equal loop inductance, all three become the same inductor above a few tens of MHz, and their anti-resonances can make the impedance worse. Prefer many identical capacitors with the lowest loop inductance, plus one bulk part for the low end.

The whole network

Use three tiers:

  • Bulk, 10–470 µF electrolytic or polymer, for the regulator's response.
  • Mid-band ceramic, 1–10 µF, for kHz to MHz.
  • Local, 10 nF or 100 nF 0402 at each supply pin, up to the knee.

Check the combined impedance against the target line, as the chart does, not the part count.

Further reading: Larry Smith & Eric Bogatin, Principles of Power Integrity for PDN Design; Howard Johnson, High-Speed Digital Design.

إصدار المحرك ⁨1.18.3⁩